Designing the Cube


64 FPGA on board
50 Capacitors per FPGA (3,276 caps on board)
over 120 connections per FPGA (over 39,000 on board)


Target internal speed: 200MHz
Target I/O speed: 100MHz


One TI PTH05030W power module per row providing 30A max. current at 1.2V for VCCINT.
Dual ATX power connectors on board.
Separated VCCINT power plane for each row.


Total 8 layers:
Top: component and routing
layer 2: VCCAUX
layer 3: VCCIO
layer 4: internal routing
layer 5: internal routing
layer 6: GND
layer 7: VCCINT, +5V, VCC1.8
Bottom: component and routing

Fall safe

Each FPGA can be programmed individually through jumper at the programing lines.
Each FPGA can access a 32 bits GPIO header for debugging.
Every two rows can be skipped through jumper setting in case any of the FPGAs on these rows failed.

Faculty of Engineering: Department of Computing
Computer Architecture