3 rd Imperial College 

Computer Systems Research Day

Sponsored by Cre8Ventures

September 25th, 2007.
Location: Read Lecture Theatre, Sherfield, number 22 on the map.

If you would like to attend, please send an email to Tanya Clark at tac_at_doc.ic.ac.uk, subject: research day and cc: oskar_at_doc.ic.ac.uk

All talks are 25 minutes, leaving 15 minutes for audience questions and discussions.

09.30 Reception, Top 9 Posters on display,

10.00 Jeff Magee (Head of Computing Department), Imperial College London,


10.05 Michael J. Flynn, Stanford University,

"Autonomous System on a Chip: the step beyond SOC"

Bio: Michael J Flynn, Professor of Electrical Engineering at Stanford University, is best-known for the development of the now familiar stream outline of computer organization (SIMD, SISD, MISD, MIMD) and the first detailed discussion of techniques for the simultaneous execution of multiple instructions, now called super scalar design. In the early 1970s Prof. Flynn founded both of the specialist organizations on Computer Architecture: the IEEE Computer Society's Technical Committee on Computer Architecture and the ACM's SIGARCH. Prof. Flynn was the 1992 recipient of the ACM/IEEE Eckert-Mauchley Award for his technical contributions to computer and digital systems architecture. He was the 1995 recipient of the IEEE-CS Harry Goode Memorial Award in recognition of his outstanding contribution to the design and classification of computer architecture.

10.40 Wayne Luk, Imperial College London,
"Self-optimising and self-verifying design: a vision"

Bio: Wayne Luk is Professor of Computer Engineering at Imperial College London where he founded and leads the Computer Systems Section, and a Visiting Professor at Stanford University and Queen's University Belfast. He is best known for his research on field-programmable technology and custom computing, such as reconfigurable system design, customisable hardware compilation, and verifiable development techniques and tools. His work has been supported by industry, by the European Commission, and by the UK Engineering and Physical Sciences Research Council, including a platform grant. He received several awards, such as a Research Excellence Award from Imperial College London in 2006, the Best Paper Award at the IEEE International Conference on Field Programmable Technology in 2005, and the Michal Servit Award at the International Conference on Field Programmable Logic and Applications in 2004. He chaired the UK Chapter of ACM Special Interest Group on Design Automation (SIGDA) during 2002-2004, and is founding co-editor-in-chief of ACM Transactions on Reconfigurable Technology and Systems and a guest editor for Journal of VLSI Signal Processing Systems.

11.20 Four Poster presentations, 1 slide, 2.5 minutes each.

11.30 - 11.40 Break

11.40 Prof. Nakamura, Tohoku University,
"It's Time to Use FPGAs in Designing Peta-Scale Supercomputers"

Bio: Tadao Nakamura received his PhD from Tohoku University in 1972. Dr. Nakamura is currently a Professor Emeritus of Tohoku University. He was a Professor of the university from 1988-2007, and sent his many PhD graduates to universities and industry. From 1994-97 he was a Visiting Professor of the Electrical Engineering Department at Stanford University. His recent research interests are in computer architecture, especially MISD computers with low-power and high-speed chips. In 2004 he received The IEEE Computer Society.s Taylor L. Booth Award. He has been Organizing Committee Chair of COOL Chips conference series fully sponsored by The IEEE Computer Society. He is an IEEE Fellow.

12.20 Viktor Prasanna, University of South California,
"FPGA based Accelerators for Scientific Computations"

Bio: Viktor K. Prasanna (V. K. Prasanna Kumar) (ceng.usc.edu/~prasanna) is Charles Lee Powell Chair in Engineering in the Ming Hsieh Department of Electrical Engineering and Professor of Computer Science at the University of Southern California. He is also an associate member of the Center for Applied Mathematical Sciences(CAMS) at USC. He served as the Division Director for the Computer Engineering Division during 1994-98. His research interests include parallel and distributed systems including networked sensor systems, embedded systems, configurable architectures and high performance computing. Dr. Prasanna has published extensively and consulted for industries in the above areas. He has served on the organizing committees of several international meetings in VLSI computations, parallel computation, and high performance computing. He is the Steering Co-chair of the International Parallel and Distributed Processing Symposium [merged IEEE International Parallel Processing Symposium(IPPS) and the Symposium on Parallel and Distributed Processing(SPDP)] and is the Steering Chair of the International Conference on High Performance Computing(HiPC). He has served on the editorial boards of the Journal of Parallel and Distributed Computing, Proceedings of the IEEE, IEEE Transactions on VLSI Systems, and IEEE Transactions on Parallel and Distributed Systems. He served as the Editor-in-Chief of the IEEE Transactions on Computers during 2003-06. He was the founding Chair of the IEEE Computer Society Technical Committee on Parallel Processing. He is a Fellow of the IEEE. He is a receipient of the 2005 Okawa Foundation Grant.

13.00 Four Poster presentations, 1 slide, 2.5 minutes each.

13.10 - 14.10 Lunch and Posters on display

14.10 Roger Woods, Queen's University, Belfast,
"Future SoC architectures and how to program them"

Bio: Roger Woods is a Professor at Queen's University Belfast and leads the Programmable Systems Laboratory. His current research interests include system-level design flows and applications of programmable systems. He was general chair of the FPL 2001 and the IEE's FPGA Developer's Forum in 2003 and 2005 and technical program committee co-chair of 2005 IEEE IWVDVT workshop and 2008 Applied Reconfigurable Conference (ARC). He is on the program committee of conferences including SIPS, FCCM, FPL, FPT, ARC and VLSIDAT. He has published over 130 scientific papers and holds a number of patents in the real-time implementation of digital filters. He is a fellow of the IET and a senior member of IEEE.

14.50 Robert Mullins, Cambridge University,
"Manycore processors: will evolution be good enough?"

Bio: Robert Mullins is an Assistant Director of Research in the Computer Laboratory and a member of the Computer Architecture Group. His research interests include computer architecture and VLSI design. Current research is focused on developing novel energy-efficient communication-centric architectures. This work includes a detailed study of on-chip interconnection networks (Network-on-Chip).

15.30 Most Cre8tive poster prizes announced by Carson Bradbury

15.40 - 15.50 Break

15.50 Cliff Young, DE Shaw Research,
"Incorporating Flexibility in Anton, a Specialized Machine for Molecular Dynamics Simulation "

Bio: Cliff Young works for D. E. Shaw Research, LLC, a member of the D. E. Shaw group of companies, on projects involving special-purpose, high-performance computers for computational biochemistry. Before his current position, he was a Member of Technical Staff at Bell Laboratories in Murray Hill, New Jersey. He received A.B., S.M., and Ph.D. degrees in computer science from Harvard University in 1989, 1995, and 1998, respectively.

16.30 Mladen Berekovic, IMEC, Belgium,
"Signal Processing on ADRES Coarse-Grain Array Processors"

Bio: Mladen Berekovic has received the Dipl.-Ing. and Dr.-Ing degrees both from the University of Hannover, Germany, in electrical and computer engineering. He has been Research Assistant with the Institute for Microelectronic Systems at the University of Hanover since 1995 where he worked on several programmable video processor chips for MPEG-4 and image processing. After working at IBM Germany on processor development he is now with IMEC where he was leading teams on reconfigurable and ultra-low power DSP processor platforms. Dr. Berekovic also works as part-time professor at the computer engineering department of TU Delft, the Netherlands. His present research interests include low-power VLSI implementations for signal processing, DSP and processor architectures and reconfigurable computing. Dr. Berekovic is a member of the IEEE and ACM, and served as a reviewer for several IEEE conferences and journal publications including DAC, IEEE Trans. CSVT and the Kluwer Journal of VLSI Signal Processing Systems. He is member of the program committees of FPL, RAW, ARC, ARCS, SAMOS and Estimedia.

17.10 Steve Furber, Manchester University,
"Living with Failure: lessons from nature"

Bio: Steve Furber is the ICL Professor of Computer Engineering in the School of Computer Science at the University of Manchester. He received his B.A. degree in Mathematics in 1974 and his Ph.D. in Aerodynamics in 1980 from the University of Cambridge, England. From 1980 to 1990 he worked in the hardware development group within the R&D department at Acorn Computers Ltd, and was a principal designer of the BBC Microcomputer and the ARM 32-bit RISC microprocessor, both of which earned Acorn Computers a Queen's Award for Technology. Upon moving to the University of Manchester in 1990 he established the Amulet research group which has interests in asynchronous logic design and power-efficient computing, and which merged with the Parallel Architectures and Languages group in 2000 to form the Advanced Processor Technologies group. The APT group is supported by an EPSRC Portfolio Partnership Award. Steve is a Fellow of the Royal Society, the Royal Academy of Engineering, the British Computer Society, the Institution of Engineering and Technology and the IEEE, and a Chartered Engineer. In 2003 he was awarded a Royal Academy of Engineering Silver Medal for "an outstanding and demonstrated personal contribution to British engineering, which has led to market exploitation". In 2004 he became the holder of a Royal Society Wolfson Research Merit Award.

17.50 Conclusion.