2nd Imperial College
Computer Systems Research Day
August 16th, 2006.
Department of Computing
Location: Exhibition Road, South Kensington, Tanaka Business School Lecture Theatres
10.00 Wayne Luk, Head of Computer Systems Section,
Department of Computing, Imperial
College London.
Welcome.
10.10 Michael J. Flynn, Stanford University.
"The representation
problem and its limitation on computation"
| Bio:
Michael J Flynn, Professor of Electrical Engineering at Stanford University, is best-known for the development of the now familiar stream outline of computer organization (SIMD, SISD, MISD, MIMD) and the first detailed discussion of techniques for the simultaneous execution of multiple instructions, now called super scalar design. In the early 1970s Prof. Flynn founded both of the specialist organizations on Computer Architecture: the IEEE Computer Society's Technical Committee on Computer Architecture and the ACM's SIGARCH. Prof. Flynn was the 1992 recipient of the ACM/IEEE Eckert-Mauchley Award for his technical contributions to computer and digital systems architecture. He was the 1995 recipient of the IEEE-CS Harry Goode Memorial Award in recognition of his outstanding contribution to the design and classification of computer architecture.
|
10.50 Tadao Nakamura, Tohoku University.
"Toward Cool Peta-Scale Computing"
| Bio:
Tadao Nakamura received his PhD in Electronics using Computer Aided
Design in 1972 from Tohoku University. Dr. Nakamura is currently a
Professor of the Department of Computer and Mathematical Sciences at
Tohoku
University. He was founding chair of the department in 1993. Prior
to
that he was a Professor of the Department of Mechanical (Machine
Intelligence and Systems) Engineering at Tohoku University and a
Visiting
Lecturer in the Department of Information Science at the University of
Tokyo. From 1994-98 he was a Visiting Professor of Electrical
Engineering
at Stanford University. His recent research interests are in
computer
architecture, especially pipelining based microarchitecture, and low
power
concepts in chips, in general. He was elected in 2004 to receive the
IEEE
Computer Society Taylor L. Booth Award. He has been Organizing
Committee
Chair of the IEEE COOL Chips conference series fully sponsored by the
IEEE
Computer Society. He was also a Program Committee member of the IEEE
HOT
Chips 15. Dr. Nakamura was elected Fellow of the IEEE in 2002 for
contributions to pipelined computer architecture and computer
engineering
education.
|
Computer Systems Research Section, Poster Session
11.40 Richard Kaufmann, High Performance Computing, HP.
"Multi-Core General Purpose Processors
and Alternative Processors: Can't we all just get along?"
| Bio:
Richard Kaufmann has been with Hewlett Packard since 1991, and is a
Distinguished Technologist in the High Performance Computing Division.
He works on hardware and systems issues that affect technical
computing
users, both for current products as well as longer-term research
projects. Previous experience includes managing C, C++ and Ada
compiler
teams at Digital Equipment Corporation and TeleSoft, Inc.. He received
a
B.A. in Computer Science at the University of California, San Diego
('78), where he was a member of the UCSD Pascal Project.
|
12.20 Mark Harris, nVidia
"General-Purpose Computating on GPUs"
| Bio:
Mark Harris is a Developer Technology Engineer at NVIDIA.
Before joining NVIDIA, he obtained a Ph.D. in computer science from the
University of North Carolina at Chapel Hill. His research interests
include general-purpose computation on GPUs, real-time computer
graphics, and physically-based simulation. Mark lives and works in
London.
|
====================================
1.00 - 2.00 Lunch and Poster Session
====================================
02.00 Cliff Young, DE Shaw Research
"Architectures and Algorithms for
Biomolecular Simulation"
| Bio:
Cliff Young works for D. E. Shaw Research, LLC, a member of the
D. E. Shaw
group of companies, on projects involving special-purpose,
high-performance
computers for computational biochemistry. Before his current
position, he
was a Member of Technical Staff at Bell Laboratories in Murray Hill,
New
Jersey. He received A.B., S.M., and Ph.D. degrees in computer science
from
Harvard University in 1989, 1995, and 1998, respectively.
|
02.40 Marco Platzner, University fo Paderborn.
"SAT, CHESS and GO: FPGAs unleashed"
| Bio:
Marco Platzner is Professor for Computer Engineering at the University
of Paderborn and member of the board
of the Paderborn Center for Parallel Computing. His research interests
include reconfigurable computing and
aspects of hardware/software codesign. After diploma and doctoral
studies in Telematics at the Graz University
of Technology, Austria, Marco Platzner held postdoc positions at the
GMD
- Research Center for Information
Technology in Sankt Augustin, Germany and at the Computer Systems Lab,
Stanford University, Palo Alto, USA.
From 1998 to 2004, Marco Platzner was with the Computer Engineering
and
Networks Lab of ETH Zurich.
Marco Platzner is a member of the IEEE and the ACM. He is also member
of
the faculty at the Advanced Learning
and Research Institute (ALaRI) of the Universita' della Svizzera
Italiana, in Lugano, Switzerland.
|
Computer Systems Research Section, Poster Session
03.30 Tsahi Birk, Technion.
"On the Judicious Exploitation of
Redundancy for Performance Enhancement"
| Bio:
Dr. Birk has been a faculty member in the Electrical Engineering
department at the Technion since 1991. He also heads its Parallel
Systems Lab. Previously, he was a research staff member at IBM's
Almaden Research Center in California. He is also involved with
industry in various ways. Dr. Birk received his B.Sc. (cum laude) and
M.Sc. from the Technion, and the PhD from Stanford University, all in
Electrical Engineering.
Dr. Birk's research interests include computer and communication
systems, in particular parallel architectures, with focus on
communication-intensive storage and information-dissemination
systems. The judicious exploitation of redundancy for performance
enhancement in various contexts has been the subject of much of his
recent work. Topics in processor architecture and systems involving
InfiniBand have also been subjects of recent research.
|
04.10 John Villasenor, UCLA.
"Rethinking Systems in Light of Novel
Non-volatile Memory Technologies"
| Bio:
John Villasenor received the B.S. degree in 1985 from the University of
Virginia, the M.S. in 1986 from Stanford University, and the Ph.D. in
1989 from Stanford, all in Electrical Engineering. From 1990 to 1992,
he was with the Jet Propulsion Laboratory in Pasadena, California. He
joined the Electrical Engineering Department at UCLA in 1992, and is
currently Professor. His research interests lie in communications,
computing, imaging, coding, and networking. |
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