Floating Point Unit Generation and Evaluation for FPGAs
[IEEE Conference on Field Programmable Custom Computing Machines, Napa, April 2003]
Jian Liang, Russell Tessier, Oskar Mencer

abstract.

Floating point units form an important component of many reconfigurable computing 
applications. The creation of floating point units under a collection of area, latency, 
and throughput constraints is an important consideration for system designers. Given 
the range of possible tradeoffs, most commercial or academic floating point libraries 
for FPGAs provide a small fraction of possible floating point units. In contrast, the 
floating unit generation approach outlined in this paper allows for the creation of 
more than 200 different floating point units, with differing area, throughput, and 
latency characteristics. These variations are supported through selection of a 
floating point architecture and the use of floating point unit pipelining. Each of 
these floating point units can be generated with a variable number of bits for the 
mantissa and the exponent. Given requirements on throughput, area and latency, our 
generation flow automatically chooses the proper algorithm and architecture to create 
a floating point unit which fulfills design requirements. Our approach is fully integrated 
into standard C++ using ASC, a stream compiler for FPGAs, and the underlying PAM-Blox II 
module generation environment [13]. The floating point units created by our approach are 
competitive in size and performance with ones created by commercial vendors.