Optimizing Hardware Function Evaluation
Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer and Wayne Luk.
[IEEE Transactions on Computers, 2005]

abstract.

We present a methodology and an automated system
for function evaluation unit generation. Our system selects the
best function evaluation hardware for a given function, accuracy
requirements, technology mapping and optimization metrics,
such as area, throughput and latency. Function evaluation f(x)
typically consists of range reduction, and the actual evaluation
on a small convenient interval such as [0, pi/2] for sin(x).

We investigate the impact of hardware function evaluation with range
reduction for a given range and precision of x and f(x) on
area and speed. An automated bit-width optimization technique
for minimizing the sizes of the operators in the data paths is
also proposed. We explore a vast design space for fixed-point
sin(x), log(x) and px accurate to one unit in the last place using
MATLAB and ASC, A Stream Compiler for Field-Programmable
Gate Arrays (FPGAs). In this study, we implement over 2000
placed-and-routed FPGA designs, resulting in over 100 million
Application-Specific Integrated Circuit (ASIC) equivalent gates.
We provide optimal function evaluation results for range and
precision combinations between 8 and 48 bits.